Conventional traction elevators include a motor, for moving the car between floors, a static drive that dictates the speed and direction of rotation of the motor, and a car logic controller that controls the drive in response to various elevator operating conditions, such as the activation of car and hall call buttons, the position of the doors, the activation of safeties and, in multiple car elevator banks, commands from the group supervisory control. When responding to a hall or car call, one of the functions of the controller is to generate speed control signals, based on a selected speed profile, to move the car quickly and smoothly to the target floor. The speed control signals are fed to the static drive which, in turn, produces an appropriate voltage and current output such that the motor rotates at the dictated speed.
Historically, solid state elevator drives were speed regulated with an analog speed reference signal. The speed reference signal was generated using analog operational amplifiers (op amps) and, generally, was normalized to 7 volts for rated speed. This signal was then compared to an actual speed signal, generated by a tachometer, and the difference was used to correct the speed of the motor. The ability to control speed accurately, however, was limited by the inherent limitations of op amps.
The problems associated with linear integrated circuits resulted in the development of new methods for generating the speed reference signal. The most reliable systems employ digital speed reference signals to control elevator speed. To do so requires transmitting signals to the static drive over a serial or parallel data transmission link.
In a typical digital speed control system today, the controller transmits to the static drive not only speed reference values, but also initial current offset signal pre-torque reference values. The latter signals are used at the beginning of a run, to pre-torque the motor prior to releasing the brake, thereby preventing unintended car movement in the interval between the time the brake is released and the time the motor begins to move the car. The speed command and pre-torque signals are stored in separate registers in the static drive microcomputer. The drive microprocessor also receives motor speed feedback signals, and generates appropriate motor control signals based upon the difference between the requested speed and the actual speed.
Each speed reference value and pre-torque reference value is in the form of a 16-bit word, which is sent to the static drive through an 8-bit parallel interface port. In order to do so, the 16-bit word is divided into two bytes: a high byte (MSB) and a low byte (LSB), which are transmitted sequentially.
Three control interface ports link the static drive and controller microprocessor: speed reference select S.sub.REF, pre-torque reference select I.sub.REF, and byte select. The controller monitors the S.sub.REF and I.sub.REF lines, and interrupts on a change from one to zero from either line. The static drive requests updates of the control signals, at predetermined time intervals, by transmitting to the controller either a speed reference select or a pre-torque reference select signal, and either a byte select high MSB or byte select low LSB signal, i.e., representing half of the 16-bit control word. The controller scales and loads the S.sub.REF and I.sub.REF values into their respective registers, and transmits the first byte of the requested parameter to the drive. The drive then changes the byte select signal, to receive the second byte (other half) of the selected parameter, and then repeats the process for the other parameter.
By way of illustration, FIG. 1 is a schematic diagram of a controller and static drive, in which the controller has scaled and loaded values of S.sub.REF and I.sub.REF, each of which is a two byte, 16-bit, twos complement number, into separate 16-bit registers. FIG. 1 illustrates the first of four load-in steps, in which the static drive sends a Speed Reference Select bit "1" to port "Speed", and a byte select bit "1" to port "Byte", in response to which the MSB of the speed control signal S.sub.REF is transmitted from the controller to the drive. The static drive processor stores the high byte in the appropriate half of the speed control register. Thereafter, the drive changes the byte select bit to "0", to load in the low byte (LSB).
After the high and low byte of the speed reference have been transmitted to the drive, the drive microprocessor requests the first byte MSB of the pre-torque value by setting the Speed select bit to "0", the Torque select bit to "1", and the Byte select bit to "1". Finally, the drive changes the byte select bit to "0" to receive the second byte (LSB) of the pre-torque reference, thus completing the process.
Each data bit port of the parallel interface just described employs an optocoupler switch, that sets the output signal at either "0" or "1", respectively as a result of a command from the controller microprocessor. The static drive has buffers at the receiving end for noise immunity. The bit ports "Byte", "Torque", and "Speed" on the static drive are controlled in the same manner, but by the drive microprocessor. Occasionally, these switches can become stuck, in which case faulty signals will be transmitted from one microprocessor to the other microprocessor.
It is therefore important to conduct periodic parallel interface integrity tests to detect any parallel interface hardware component failure. Presently, such tests are performed when the elevator is first powered up (approximately 15 seconds after main power initialization, which is the time necessary to give the elevator controller and static drive processors time to initialize their individual systems), and also when the elevator is in a stopped condition.
In performing the integrity test, the controller stores a zero speed request in the S.sub.REF register, and the one's complement of the zero speed request in the I.sub.REF register, as shown in FIG. 2. Each byte is then transmitted to the controller, and the controller verifies that the I.sub.REF is in fact the ones complement of S.sub.REF. If for six consecutive readings an error is detected, the system shuts down.
There are a number of drawbacks to the present system. If the byte select line from the drive is stuck, the high byte or low byte would be read twice during the integrity test. However, because the value of the high byte and the low byte are the same, the failure of the byte select line would not be detected.
Another drawback of the present system is that any failure during a run condition would not be detected until the car comes to a stop. If a data bit stuck high during a down run, the magnitude of the reference error may be small enough to allow the car to come into the floor for a normal slowdown and landing. However, prior to dropping the brake, when the controller dictates zero speed, if a data bit is stuck high, the speed request detected by the static drive could be as much as 200% of rated speed.